Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention relates to an arithmetic unit and memory system for an electronic calculator or microprocessor. An entire electronic calculator system including the arithmetic unit and memory system of this invention is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, the invention disclosed is not limited to that type calculator. In the prior art, such as that exemplified by the calculator disclosed in U.S. Pat. No. 3,919,532, a plurality of AND and OR logic gates have been utilized for transferring data between the operational registers and the arithmetic unit of a calculator. Further the logic gates were arranged such that only particular pairs of the operational registers could be inputted to the arithmetic unit at the same time.
It was one object of this invention therefore to provide register selector gates interconnecting the calculator memory, i.e., the calculators operational registers, with the inputs of the arithmetic unit. It was another object of this invention to permit this data stored in any two of the operational registers to be inputted to the arithmetic unit at the same time.
It is yet another object of this invention to permit the data outputted from the arithmetic unit to be inputted to a selected one of either of the two registers providing inputs to the arithmetic unit. It is still another object of this invention to simplify the register selector gates by using MOS transfer gates for interconnecting the operational registers with the inputs of the adder as opposed to using the more complex AND and OR logic gates of the prior art.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, an arithmetic unit and memory system including a plurality of selector gates are implemented on a seimconductor chip. The memory preferably comprises a plurality of operational registers and the arithmetic unit preferably has two inputs and an output and performs arithmetic operations on data received at the inputs and communicates the results thereof to the output. The operational registers and the inputs of the arithmetic unit are interconnected by a plurality of operational register selector gates arranged to permit any selected two of the plurality of operational registers to be connected to the input of the arithmetic unit. Further, additional selector gates are preferably provided for interconnecting the output of the arithmetic unit with a selected one of the operational registers connected to the inputs of the arithmetic unit. Still further, in a preferred embodiment of the invention, the aforementioned selector gates comprised simple MOS transfer gates as opposed to more complex AND/or OR logic gates.